DVCC based Readout Circuitry for Water Quality Monitoring System

A new configuration realizing water quality monitoring device using ISFET involving CMOS differential voltage current conveyor (DVCC) based low pass filter free from trans-conductance variation using Low-voltage PMOS bulkdriven cascade current mirror (P MOS BDCCM) current mirrors is proposed. The circuit uses four DVCCs as active elements and together with two capacitors and five resistors as passive elements, only one current mirror. The use of this active component makes the implementation simple and attractive. The functionality of the circuit is tested using Tanner simulator version 15 for a 70nm CMOS process model also the transfer function realization is done on MATLAB R2011a version, the Very high speed integrated circuit Hardware description language(VHDL) code for the same scheme is simulated on Xilinx ISE 10.1 and various simulation results are obtained. Simulation results are included to demonstrate the results.